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TSV Clean
TSV RESIST AND RESIDUE REMOVAL 3D integration is the most active methodology for increasing device performance. The ability to create Through Silicon Vias (TSV) provides the shortest path for interconnections and will result in increased device speed and reduced package footprint. There are many approaches and process flows for creating TSVs. These include Via-First, Via-Middle, Via-Last, Via After Bonding. The size and aspect ratio of the via will vary depending upon when the via is formed. The creation of the via by a Deep Reactive Ion Etch Process (DRIE) and the need to clean post etch is required for all scenarios.
CDE-ResMap
- Four Point Probe - Resistivity Mapping Systems
VLSI Standards Incorporated
- ACCURATE standards - traceable to SI units through NIST
- 30 YEARS of innovation supporting the ITRS road map
- The ANSWER to your quality plan
- 5 CATEGORY Products and Recertification
Wafer Roughness Measurement

FlatMaster Ra

-White light interferometer

-Roughness Measurement

Wafer transition zone Measurement

UltraSort Roll-off Measurement

- Advanced Optical Measurement of Wafer Transition Zone
ENERGETIQ
20 watt EUV source

Unique patented electrodeless Z-Pinch technology

- Low debris / low consumable cost > 10 kHz pulse rate - Enables high volume manufacturing (HVM) simulation > Small plasma size - Below 1mm diameter
AZ Electronic Material
KLEBOSOL (Colloidal Silica)

High stability for dispersion

Sharp size distribution

Easy to handle

Intego

- ARGO : Wafer, cells and glass inspection

- AOUILA : SiC wafer inspection

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