웨스트팩

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리스트 게시판
PR Coater & Developer
Automatic Coater/Developer/Bake system
Environics
- Fast Loop Design
- Teflon Rotary Valves
- Minimal Dead Volume
- Rapid Sample Switching
- User Defined Sample Sequencing
- Quick Connects for New Samples
Mask(Reticle) Flatness Measurement
- Quartz(Glass) non-contact flatness measurement system
- Blank, Pellicle mounted mask and EUV mask
- FM200Mask, UltraFlat
Single Wafer Wet Processing
- Cleaning Processors
- Solvent Processors
- Wet Etch Processors
- Developer
- Spin & Spray Coater with Bake Processing
LED Metal Lift Off
Dry-in/-out Solvent Strip and Lift-off Processing SSEC combines immersion batch soak and single wafer spray solvent processing in one completely enclosed, fully automatic system. The chart below includes applications for SI wafers and III-V semiconductors including GaAs, InP, GaN, GaP, sapphire, and SiC and glass wafers.
TSV Clean
TSV RESIST AND RESIDUE REMOVAL 3D integration is the most active methodology for increasing device performance. The ability to create Through Silicon Vias (TSV) provides the shortest path for interconnections and will result in increased device speed and reduced package footprint. There are many approaches and process flows for creating TSVs. These include Via-First, Via-Middle, Via-Last, Via After Bonding. The size and aspect ratio of the via will vary depending upon when the via is formed. The creation of the via by a Deep Reactive Ion Etch Process (DRIE) and the need to clean post etch is required for all scenarios.
Tropel Metrology - MSP
Tropel Metrology - MSP
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